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“Probabilistic” CMOS

I was intrigued by reports of ultra-efficient chips based on the probabilistic logicPCMOS. After some googling I found this pdf, which clear the subject somehow. It seems probabilistic logic is not went into equation. Instead this architecture suggest normal, deterministic CPU with probabilistic coprocessor. Coprocessor use noise as source for random number generator (essentially analog random number generator), and can use this random number generator in different Monte-Carlo algorithms, like random neural networks, probabilistic cellular automata and likes. It seems to me the gain could be achived only for specific applications which use random number generators. In this PCMOS is not different from GPU, DSP and other task-specific accelerators.

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12, February, 2009 - Posted by | Uncategorized | ,

1 Comment

  1. […] require more energy, and eating device battery very fast. One way to work around the problem is to use different, task specific architecture for CPU units/coprocessors, thus to get more processing power with the same power consumption. Another – get more energy. […]

    Pingback by More on the battery life - solar powered phone « Mirror Image | 20, February, 2009


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